1.Field of the Invention
The present invention is related to a test vector generation method and a program for automatically generating test vectors for use in testing whether or not instructions are implemented in a processor in agreement with the predetermined specifications of the instruction set architecture (ISA), and a test method and a chip manufacturing method making use of the test vectors as generated by the test vector generation method.
2. Description of the Related Art
In the past, the operation of a processor has been tested to confirm implementation of instructions in the processor in agreement with the predetermined specification, for example, (1) by manually preselecting a variety of combinations of operand values and handcoding test vectors with the combinations, or (2) by automatically generating combinations of operand values at random and then generating test vectors with the combinations. However, in accordance with the above described method (1), a considerable time is required for generating test vectors. On the other hand, in accordance with the above described method (2), a considerable time is required for completing a test program because the reliability of test program must be enhanced by making use of a large number of combinations of test vectors while each combination can be easily generated.